BIBFRAME Work

Title

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Type

  • Text
  • Monograph

Contribution

Subject

Language

Classification

Content

Summary

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

Table of Contents

Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.

Authorized Access Point

Wang, Zheng. High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Admin Metadata

  • Date: 2026-09-11T20:16:25.710522+00:00
  • Agent: cbc
  • Status: c
  • Derived from: 21739781

Admin Metadata

  • Date: 2026-09-11
  • Cataloger id: Unknown
  • Description level: http://id.loc.gov/ontologies/bibframe-2-6-0/
  • Description language: eng
  • Description authentication: pcc

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