BIBFRAME Work

Title

Memory Controllers for Mixed-Time-Criticality Systems

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  • Monograph
  • Text

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Summary

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, id est mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Table of Contents

Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.

Authorized Access Point

Goossens, Sven. Memory Controllers for Mixed-Time-Criticality Systems

Admin Metadata

  • Date: 2026-09-11T20:12:53.243802+00:00
  • Agent: cbc
  • Status: c
  • Derived from: 21737544

Admin Metadata

  • Date: 2026-09-11
  • Cataloger id: Unknown
  • Description level: http://id.loc.gov/ontologies/bibframe-2-6-0/
  • Description language: eng
  • Description authentication: pcc

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